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This isn't fully mixed but rather it supports VHDL modiles in a verilog
simulation. You can't have verilog undernearth the VHDL either. It
uses the ghdl (v3 or higher) synth option to synth the VHDL top modules
to verilog and then it uses those with Icarus.
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Uses icarus verilog and gtkwave to simulate a simple counter.
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Add a top simulation file and add comments in the makefile for it. This
allows an input file from Octave and output a file to generate a graph.
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The core was missing a data ready signal so I added one. Going to be
needed for file I/O for simulation.
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Need to do more testing, possibly some Octave input and output.
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freq_graph_generator is a executable GNU Octave script that generates
a graph of the dft from an input file. This is useful for testing
filters with impulses and then seeing their frequency response.
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A simple GNU Octave executable script that generates intput files for
filter testing.
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