counter: simple simulation of a countercounter

4 files changed, 217 insertions, 0 deletions

diff --git a/counter/Makefile b/counter/Makefile
new file mode 100644
index 0000000..da512e5
--- /dev/null
+++ b/counter/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2023 Brian Woods
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# this is for ghdl-gcc, I've not tested it on ghdl-llvm but it will not
+# work with ghdl-mcode
+
+SRC=simulation.vhd top.vhd counter.vhd
+OBJ=$(SRC:.vhd=.o)
+TOP=simulation
+TOP_OBJ=e~$(TOP).o
+WAVE=simulation.ghw
+WORKLIB=work
+FLAGS=--std=08 --work=$(WORKLIB)
+TIME=1us
+
+.PHONY: all clean sim
+
+all: $(TOP)
+
+%.o: %.vhd
+	ghdl -a $(FLAGS) $<
+
+$(TOP): $(OBJ)
+	ghdl -e $(FLAGS) $@
+
+$(WAVE): $(TOP)
+	ghdl -r $(FLAGS) $< --wave=$@ --stop-time=$(TIME)
+
+sim: $(WAVE)
+	 gtkwave $<
+
+clean:
+	rm -f $(OBJ) $(TOP_OBJ) $(TOP) $(WAVE) $(WORKLIB)-obj*.cf
diff --git a/counter/counter.vhd b/counter/counter.vhd
new file mode 100644
index 0000000..d4a941b
--- /dev/null
+++ b/counter/counter.vhd
@@ -0,0 +1,36 @@
+-- SPDX-FileCopyrightText: 2023 Brian Woods
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity counter is
+	port(
+		set: in std_logic;
+		set_val: in unsigned(7 downto 0);
+		cnt: out unsigned(7 downto 0);
+		en: in  std_logic;
+		clr: in std_logic;
+		clk: in std_logic
+	);
+end entity;
+
+architecture func of counter is
+	signal counter: unsigned(7 downto 0);
+begin
+	cnt <= counter;
+
+	process (clk, clr)
+	begin
+		if (clr='1') then
+			counter <= "00000000";
+		elsif  (clk='1' and clk'event) then
+			if (set='1') then
+				counter <= set_val;
+			elsif (en='1') then
+				counter <= counter + 1;
+			end if;
+		end if;
+	end process;
+end func;
diff --git a/counter/simulation.vhd b/counter/simulation.vhd
new file mode 100644
index 0000000..4fbb228
--- /dev/null
+++ b/counter/simulation.vhd
@@ -0,0 +1,97 @@
+-- SPDX-FileCopyrightText: 2023 Brian Woods
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity simulation is
+end;
+
+architecture sim of simulation is
+	component top is
+	port(
+		set: in std_logic;
+		set_val: in unsigned(7 downto 0);
+		cnt: out unsigned(7 downto 0);
+		en: in  std_logic;
+		clr: in std_logic;
+		cnt_auto: out unsigned(7 downto 0);
+		clk: in std_logic
+	);
+	end component;
+
+	signal set: std_logic := '0';
+	signal set_val: unsigned(7 downto 0) := "00000000";
+	signal cnt: unsigned(7 downto 0);
+	signal en:  std_logic := '0';
+	signal clr: std_logic := '0';
+	signal cnt_auto: unsigned(7 downto 0);
+	signal clk: std_logic := '0';
+begin
+	dut: top port map(
+		set => set,
+		set_val => set_val,
+		cnt => cnt,
+		en => en,
+		clr => clr,
+		cnt_auto => cnt_auto,
+		clk => clk
+	);
+
+	clk <= not clk after 5 ns;
+	-- clr <= '1', '0' after 20 ns;
+	-- en  <= '0', '1' after 10 ns;
+
+	-- clk_proc: process begin
+	-- begin
+	-- end process clk_proc;
+
+	process begin
+		-- at 0 ns
+		set <= '0';
+		set_val <= "00000000";
+		en <= '0';
+		clr <= '1';
+		wait for 10 ns;
+
+		-- at 10 ns
+		set <= '0';
+		set_val <= "00000000";
+		en <= '1';
+		clr <= '1';
+		wait for 10 ns;
+
+		-- at 20 ns
+		set <= '0';
+		set_val <= "00000000";
+		en <= '1';
+		clr <= '0';
+		wait for 80 ns;
+
+		-- at 100 ns
+		set <= '1';
+		set_val <= "00100000";
+		en <= '1';
+		clr <= '0';
+		wait for 10 ns;
+
+		-- at 110 ns
+		set <= '0';
+		set_val <= "00000000";
+		en <= '1';
+		clr <= '0';
+		wait for 100 ns;
+
+		-- at 210 ns
+		set <= '0';
+		set_val <= "00000000";
+		en <= '0';
+		clr <= '0';
+		wait for 10 ns;
+
+		-- end sim
+		wait;
+	end process;
+
+end sim;
diff --git a/counter/top.vhd b/counter/top.vhd
new file mode 100644
index 0000000..2ae4216
--- /dev/null
+++ b/counter/top.vhd
@@ -0,0 +1,51 @@
+-- SPDX-FileCopyrightText: 2023 Brian Woods
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity top is
+	port(
+		set: in std_logic;
+		set_val: in unsigned(7 downto 0);
+		cnt: out unsigned(7 downto 0);
+		en: in  std_logic;
+		cnt_auto: out unsigned(7 downto 0);
+		clr: in std_logic;
+		clk: in std_logic
+	);
+end entity;
+
+architecture func of top is
+	component counter is
+	port(
+		set: in std_logic;
+		set_val: in unsigned(7 downto 0);
+		cnt: out unsigned(7 downto 0);
+		en: in  std_logic;
+		clr: in std_logic;
+		clk: in std_logic
+	);
+	end component;
+begin
+	-- controlled by the top signals
+	counter01: counter port map(
+		set => set,
+		set_val => set_val,
+		cnt => cnt,
+		en => en,
+		clr => clr,
+		clk => clk
+	);
+
+	-- just counts automatically
+	counter02: counter port map(
+		set => '0',
+		set_val => "00000000",
+		cnt => cnt_auto,
+		en => '1',
+		clr => clr,
+		clk => clk
+	);
+end func;