counter_v: add counter example in verilog

Uses icarus verilog and gtkwave to simulate a simple counter.

4 files changed, 84 insertions, 0 deletions

diff --git a/counter_v/Makefile b/counter_v/Makefile
new file mode 100644
index 0000000..9f096cd
--- /dev/null
+++ b/counter_v/Makefile
@@ -0,0 +1,29 @@
+# SPDX-FileCopyrightText: 2023 Brian Woods
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# this is for ghdl-gcc, I've not tested it on ghdl-llvm but it will not
+# work with ghdl-mcode
+
+SRC=simulation.v top.v counter.v
+# top module, we also use this for the object name
+TOP=sim_test
+# this needs to match what's in top sim file
+WAVE_DUMP=simulation.vcd
+WAVE_CONF=$(TOP).gtkw
+FLAGS=
+
+.PHONY: all clean sim
+
+all: $(TOP)
+
+$(TOP): $(SRC)
+	iverilog -o $@ $(FLAGS) -s $@ $^
+
+$(WAVE_DUMP): $(TOP)
+	vvp $<
+
+sim: $(WAVE_DUMP)
+	gtkwave --save $(WAVE_CONF) --saveonexit $<
+
+clean:
+	rm -f $(TOP) $(WAVE_DUMP) $(WAVE_CONF)
diff --git a/counter_v/counter.v b/counter_v/counter.v
new file mode 100644
index 0000000..79e55df
--- /dev/null
+++ b/counter_v/counter.v
@@ -0,0 +1,17 @@
+module counter(out, clk, reset);
+
+  parameter WIDTH = 8;
+
+  output [WIDTH-1: 0] out;
+  input	     clk, reset;
+
+  reg [WIDTH-1: 0]   out;
+  wire       clk, reset;
+
+  always @(posedge clk or posedge reset)
+    if (reset)
+      out <= 0;
+    else
+      out <= out + 1;
+
+endmodule // counter
diff --git a/counter_v/simulation.v b/counter_v/simulation.v
new file mode 100644
index 0000000..1dfbf25
--- /dev/null
+++ b/counter_v/simulation.v
@@ -0,0 +1,27 @@
+module sim_test;
+
+  /* Make a reset that pulses once. */
+  reg reset = 0;
+  initial begin
+     $dumpfile("simulation.vcd");
+     $dumpvars(0, sim_test);
+
+     # 17 reset = 1;
+     # 11 reset = 0;
+     # 29 reset = 1;
+     # 11 reset = 0;
+     //# 100 $stop;
+     # 200 $finish;
+  end
+
+  /* Make a regular pulsing clock. */
+  reg clk = 0;
+  always #5 clk = !clk;
+
+  wire [5:0] value;
+  top top_logic (value, clk, reset);
+
+  initial
+     $monitor("At time %t, value = %h (%0d)",
+              $time, value, value);
+endmodule // sim_test
diff --git a/counter_v/top.v b/counter_v/top.v
new file mode 100644
index 0000000..02b9bc6
--- /dev/null
+++ b/counter_v/top.v
@@ -0,0 +1,11 @@
+module top(count, clk, reset);
+
+	parameter WIDTH = 6;
+
+	output [WIDTH-1: 0] count;
+	input  clk, reset;
+
+	wire [WIDTH-1:0] value;
+	counter #(WIDTH) counter_1 (count, clk, reset);
+
+endmodule // top