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author | Brian Woods | 2023-03-23 22:30:40 -0400 |
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committer | Brian Woods | 2023-03-23 22:39:44 -0400 |
commit | 2e5b437fc94aa989ca81aa820739178281d218d8 (patch) | |
tree | e4810865577993efb28545d914ad7b01e8ba58f7 /counter_v/top.v | |
parent | ac193d21bf29672513afbab5102708e0d4fee61e (diff) |
counter_v: add counter example in verilog
Uses icarus verilog and gtkwave to simulate a simple counter.
Diffstat (limited to 'counter_v/top.v')
-rw-r--r-- | counter_v/top.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/counter_v/top.v b/counter_v/top.v new file mode 100644 index 0000000..02b9bc6 --- /dev/null +++ b/counter_v/top.v @@ -0,0 +1,11 @@ +module top(count, clk, reset); + + parameter WIDTH = 6; + + output [WIDTH-1: 0] count; + input clk, reset; + + wire [WIDTH-1:0] value; + counter #(WIDTH) counter_1 (count, clk, reset); + +endmodule // top |