From 2e5b437fc94aa989ca81aa820739178281d218d8 Mon Sep 17 00:00:00 2001
From: Brian Woods
Date: Thu, 23 Mar 2023 22:30:40 -0400
Subject: counter_v: add counter example in verilog

Uses icarus verilog and gtkwave to simulate a simple counter.
---
 counter_v/top.v | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 counter_v/top.v

(limited to 'counter_v/top.v')

diff --git a/counter_v/top.v b/counter_v/top.v
new file mode 100644
index 0000000..02b9bc6
--- /dev/null
+++ b/counter_v/top.v
@@ -0,0 +1,11 @@
+module top(count, clk, reset);
+
+	parameter WIDTH = 6;
+
+	output [WIDTH-1: 0] count;
+	input  clk, reset;
+
+	wire [WIDTH-1:0] value;
+	counter #(WIDTH) counter_1 (count, clk, reset);
+
+endmodule // top
-- 
cgit v1.2.3