counter_v: add counter example in verilog

Uses icarus verilog and gtkwave to simulate a simple counter.

1 files changed, 17 insertions, 0 deletions

diff --git a/counter_v/counter.v b/counter_v/counter.v
new file mode 100644
index 0000000..79e55df
--- /dev/null
+++ b/counter_v/counter.v
@@ -0,0 +1,17 @@
+module counter(out, clk, reset);
+
+  parameter WIDTH = 8;
+
+  output [WIDTH-1: 0] out;
+  input	     clk, reset;
+
+  reg [WIDTH-1: 0]   out;
+  wire       clk, reset;
+
+  always @(posedge clk or posedge reset)
+    if (reset)
+      out <= 0;
+    else
+      out <= out + 1;
+
+endmodule // counter