From 2e5b437fc94aa989ca81aa820739178281d218d8 Mon Sep 17 00:00:00 2001
From: Brian Woods
Date: Thu, 23 Mar 2023 22:30:40 -0400
Subject: counter_v: add counter example in verilog

Uses icarus verilog and gtkwave to simulate a simple counter.
---
 counter_v/counter.v | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 counter_v/counter.v

(limited to 'counter_v/counter.v')

diff --git a/counter_v/counter.v b/counter_v/counter.v
new file mode 100644
index 0000000..79e55df
--- /dev/null
+++ b/counter_v/counter.v
@@ -0,0 +1,17 @@
+module counter(out, clk, reset);
+
+  parameter WIDTH = 8;
+
+  output [WIDTH-1: 0] out;
+  input	     clk, reset;
+
+  reg [WIDTH-1: 0]   out;
+  wire       clk, reset;
+
+  always @(posedge clk or posedge reset)
+    if (reset)
+      out <= 0;
+    else
+      out <= out + 1;
+
+endmodule // counter
-- 
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