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author | Brian Woods | 2023-02-24 12:17:46 -0500 |
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committer | Brian Woods | 2023-02-24 13:20:19 -0500 |
commit | d7a11e0e8584e088921c9486c4f064eaf5e004f7 (patch) | |
tree | d82a56d3c0fc9e1434aa6cc514f7616bc4c5c092 /counter/counter.vhd | |
parent | 353910fa6f1ef1b1eed5b8c4db6d528e521ce127 (diff) |
counter: simple simulation of a countercounter
Diffstat (limited to 'counter/counter.vhd')
-rw-r--r-- | counter/counter.vhd | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/counter/counter.vhd b/counter/counter.vhd new file mode 100644 index 0000000..d4a941b --- /dev/null +++ b/counter/counter.vhd @@ -0,0 +1,36 @@ +-- SPDX-FileCopyrightText: 2023 Brian Woods +-- SPDX-License-Identifier: GPL-2.0-or-later + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity counter is + port( + set: in std_logic; + set_val: in unsigned(7 downto 0); + cnt: out unsigned(7 downto 0); + en: in std_logic; + clr: in std_logic; + clk: in std_logic + ); +end entity; + +architecture func of counter is + signal counter: unsigned(7 downto 0); +begin + cnt <= counter; + + process (clk, clr) + begin + if (clr='1') then + counter <= "00000000"; + elsif (clk='1' and clk'event) then + if (set='1') then + counter <= set_val; + elsif (en='1') then + counter <= counter + 1; + end if; + end if; + end process; +end func; |