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author | Brian Woods | 2023-03-23 22:30:40 -0400 |
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committer | Brian Woods | 2023-03-23 22:39:44 -0400 |
commit | 2e5b437fc94aa989ca81aa820739178281d218d8 (patch) | |
tree | e4810865577993efb28545d914ad7b01e8ba58f7 /counter_v/simulation.v | |
parent | ac193d21bf29672513afbab5102708e0d4fee61e (diff) |
counter_v: add counter example in verilog
Uses icarus verilog and gtkwave to simulate a simple counter.
Diffstat (limited to 'counter_v/simulation.v')
-rw-r--r-- | counter_v/simulation.v | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/counter_v/simulation.v b/counter_v/simulation.v new file mode 100644 index 0000000..1dfbf25 --- /dev/null +++ b/counter_v/simulation.v @@ -0,0 +1,27 @@ +module sim_test; + + /* Make a reset that pulses once. */ + reg reset = 0; + initial begin + $dumpfile("simulation.vcd"); + $dumpvars(0, sim_test); + + # 17 reset = 1; + # 11 reset = 0; + # 29 reset = 1; + # 11 reset = 0; + //# 100 $stop; + # 200 $finish; + end + + /* Make a regular pulsing clock. */ + reg clk = 0; + always #5 clk = !clk; + + wire [5:0] value; + top top_logic (value, clk, reset); + + initial + $monitor("At time %t, value = %h (%0d)", + $time, value, value); +endmodule // sim_test |