counter_v/counter.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

module counter(out, clk, reset);

  parameter WIDTH = 8;

  output [WIDTH-1: 0] out;
  input	     clk, reset;

  reg [WIDTH-1: 0]   out;
  wire       clk, reset;

  always @(posedge clk or posedge reset)
    if (reset)
      out <= 0;
    else
      out <= out + 1;

endmodule // counter