mixed_hdl: add init filesHEADmaster

This isn't fully mixed but rather it supports VHDL modiles in a verilog
simulation.  You can't have verilog undernearth the VHDL either.  It
uses the ghdl (v3 or higher) synth option to synth the VHDL top modules
to verilog and then it uses those with Icarus.

1 files changed, 23 insertions, 0 deletions

diff --git a/mixed_hdl/counter.v b/mixed_hdl/counter.v
new file mode 100644
index 0000000..23ab9f2
--- /dev/null
+++ b/mixed_hdl/counter.v
@@ -0,0 +1,23 @@
+module counter(count, dr, en, rst, clk);
+
+	parameter WIDTH = 8;
+
+	output [WIDTH-1: 0] count;
+	output dr;
+	input  en, rst, clk;
+
+	reg [WIDTH-1: 0]   count;
+	wire     en, rst, clk;
+	reg dr;
+
+	always @(posedge clk or posedge rst)
+	begin
+		if (rst)
+			count <= 0;
+		else
+			dr <= en;
+			if (en)
+				count <= count + 1;
+	end
+
+endmodule // counter