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| author | Brian Woods | 2023-04-12 12:55:22 -0400 |
|---|---|---|
| committer | Brian Woods | 2023-04-12 12:55:22 -0400 |
| commit | 68083e9e02744022631d5b77e119f8d0fcb306b8 (patch) | |
| tree | 2269ea10e709218a12b2854af8dcacb6e72a0696 /helper_scripts/input_generator | |
| parent | 2e5b437fc94aa989ca81aa820739178281d218d8 (diff) | |
This isn't fully mixed but rather it supports VHDL modiles in a verilog
simulation. You can't have verilog undernearth the VHDL either. It
uses the ghdl (v3 or higher) synth option to synth the VHDL top modules
to verilog and then it uses those with Icarus.
Diffstat (limited to 'helper_scripts/input_generator')
0 files changed, 0 insertions, 0 deletions