From d7a11e0e8584e088921c9486c4f064eaf5e004f7 Mon Sep 17 00:00:00 2001
From: Brian Woods
Date: Fri, 24 Feb 2023 12:17:46 -0500
Subject: counter: simple simulation of a counter

---
 counter/top.vhd | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 counter/top.vhd

(limited to 'counter/top.vhd')

diff --git a/counter/top.vhd b/counter/top.vhd
new file mode 100644
index 0000000..2ae4216
--- /dev/null
+++ b/counter/top.vhd
@@ -0,0 +1,51 @@
+-- SPDX-FileCopyrightText: 2023 Brian Woods
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity top is
+	port(
+		set: in std_logic;
+		set_val: in unsigned(7 downto 0);
+		cnt: out unsigned(7 downto 0);
+		en: in  std_logic;
+		cnt_auto: out unsigned(7 downto 0);
+		clr: in std_logic;
+		clk: in std_logic
+	);
+end entity;
+
+architecture func of top is
+	component counter is
+	port(
+		set: in std_logic;
+		set_val: in unsigned(7 downto 0);
+		cnt: out unsigned(7 downto 0);
+		en: in  std_logic;
+		clr: in std_logic;
+		clk: in std_logic
+	);
+	end component;
+begin
+	-- controlled by the top signals
+	counter01: counter port map(
+		set => set,
+		set_val => set_val,
+		cnt => cnt,
+		en => en,
+		clr => clr,
+		clk => clk
+	);
+
+	-- just counts automatically
+	counter02: counter port map(
+		set => '0',
+		set_val => "00000000",
+		cnt => cnt_auto,
+		en => '1',
+		clr => clr,
+		clk => clk
+	);
+end func;
-- 
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