From ac193d21bf29672513afbab5102708e0d4fee61e Mon Sep 17 00:00:00 2001
From: Brian Woods
Date: Mon, 27 Feb 2023 12:37:16 -0500
Subject: averaging_filter: Add Octave simulation top file

Add a top simulation file and add comments in the makefile for it.  This
allows an input file from Octave and output a file to generate a graph.
---
 averaging_filter/Makefile              |   3 +-
 averaging_filter/simulation_octave.vhd | 106 +++++++++++++++++++++++++++++++++
 2 files changed, 108 insertions(+), 1 deletion(-)
 create mode 100644 averaging_filter/simulation_octave.vhd

diff --git a/averaging_filter/Makefile b/averaging_filter/Makefile
index 69a09ca..d29a152 100644
--- a/averaging_filter/Makefile
+++ b/averaging_filter/Makefile
@@ -4,6 +4,7 @@
 # this is for ghdl-gcc, I've not tested it on ghdl-llvm but it will not
 # work with ghdl-mcode
 
+# use simulation_octave.vhd for file I/O
 SRC=simulation.vhd top.vhd averaging_filter.vhd
 OBJ=$(SRC:.vhd=.o)
 TOP=simulation
@@ -12,7 +13,7 @@ WAVE_DUMP=$(TOP).ghw
 WAVE_CONF=$(TOP).gtkw
 WORKLIB=work
 FLAGS=--std=08 --work=$(WORKLIB)
-TIME=1us
+TIME=12us
 
 .PHONY: all clean sim
 
diff --git a/averaging_filter/simulation_octave.vhd b/averaging_filter/simulation_octave.vhd
new file mode 100644
index 0000000..65d59cc
--- /dev/null
+++ b/averaging_filter/simulation_octave.vhd
@@ -0,0 +1,106 @@
+-- SPDX-FileCopyrightText: 2023 Brian Woods
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use std.textio.all;
+
+entity simulation is
+end;
+
+architecture sim of simulation is
+	component top is
+	port(
+		input: in signed(17 downto 0);
+		output: out signed(17 downto 0);
+		en: in std_logic;
+		dr: out std_logic;
+		clr: in std_logic;
+		clk: in std_logic
+	);
+	end component;
+
+	signal input: signed(17 downto 0) := (others => '0');
+	signal output: signed(17 downto 0);
+	signal en:  std_logic := '0';
+	signal dr:  std_logic := '0';
+	signal clr: std_logic := '1';
+	signal clk: std_logic := '0';
+	signal int_input: integer := 0;
+	signal int_output: integer;
+
+begin
+	dut: top port map(
+		input => input,
+		output => output,
+		en => en,
+		dr => dr,
+		clr => clr,
+		clk => clk
+	);
+
+	clk <= not clk after 5 ns;
+
+	int_output <= to_integer(output);
+	--int_output <= 42;
+	input <= to_signed(int_input, input'length);
+
+	input_proc: process
+		file read_file: text open read_mode is "sim_input.txt";
+		variable read_line: line;
+		variable read_input: integer;
+	begin
+		-- at 0 ns
+		int_input <= 0;
+		en <= '0';
+		clr <= '1';
+		wait for 10 ns;
+
+		-- at 10 ns
+		int_input <= 0;
+		en <= '0';
+		clr <= '1';
+		wait for 10 ns;
+
+		-- at 20 ns
+		int_input <= 0;
+		en <= '0';
+		clr <= '0';
+		wait for 10 ns;
+
+		while not endfile(read_file) loop
+			readline(read_file, read_line);
+			read(read_line, read_input);
+
+			int_input <= read_input;
+			en <= '1';
+			clr <= '0';
+			wait for 10 ns;
+		end loop;
+
+		--wait for anything to happen
+		int_input <= 0;
+		en <= '0';
+		clr <= '0';
+		wait for 100 ns;
+
+		-- end sim
+		wait;
+	end process;
+
+	-- for writing output to a file
+	output_proc: process(clk, dr)
+		file write_file: text open write_mode is "sim_output.txt";
+		variable write_line: line;
+		variable write_output: integer;
+	begin
+		if (clk='1' and clk'event) then
+			if (dr='1') then
+				write_output := int_output;
+				write(write_line, write_output);
+				writeline(write_file, write_line);
+			end if;
+		end if;
+	end process;
+end sim;
-- 
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