From 84a6b2e55134ef392aa068c38f1981ead54e7a4b Mon Sep 17 00:00:00 2001
From: Brian Woods
Date: Fri, 24 Feb 2023 18:13:22 -0500
Subject: averaging_filter: added data ready signal

The core was missing a data ready signal so I added one.  Going to be
needed for file I/O for simulation.
---
 averaging_filter/averaging_filter.vhd |  9 +++++----
 averaging_filter/simulation.vhd       | 15 ++++++++++++---
 averaging_filter/top.vhd              |  7 +++++--
 3 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/averaging_filter/averaging_filter.vhd b/averaging_filter/averaging_filter.vhd
index 3792d96..e6dcfd8 100644
--- a/averaging_filter/averaging_filter.vhd
+++ b/averaging_filter/averaging_filter.vhd
@@ -17,15 +17,14 @@ entity averaging_filter is
 	port(
 		input: in signed(data_width-1 downto 0);
 		output: out signed(data_width-1 downto 0);
-		en: in  std_logic;
+		en: in std_logic;
+		dr: out std_logic;
 		clr: in std_logic;
 		clk: in std_logic
 	);
 end entity;
 
 architecture func of averaging_filter is
-	--constant overflow_buffer: integer :=
-	--    integer(ceil(log2(averaging_amount)));
 	type data_array_type is
 	    array (0 to averaging_amount-1) of
 	    signed(data_width-1 downto 0);
@@ -37,16 +36,18 @@ begin
 		if (clr='1') then
 			data_array <= (others => (others => '0'));
 			running_sum <= (others => '0');
+			dr <= '0';
 		elsif  (clk='1' and clk'event) then
 			if (en='1') then
 				running_sum <= running_sum -
 				    resize(data_array(averaging_amount-1),
-				                      running_sum'length) +
+				           running_sum'length) +
 				    resize(input, running_sum'length);
 				data_array(1 to averaging_amount-1) <=
 				    data_array(0 to averaging_amount-2);
 				data_array(0) <= input;
 			end if;
+			dr <= en;
 		end if;
 	end process;
 	output <= running_sum(data_width + overflow_buffer - 1
diff --git a/averaging_filter/simulation.vhd b/averaging_filter/simulation.vhd
index a341f48..0be98e7 100644
--- a/averaging_filter/simulation.vhd
+++ b/averaging_filter/simulation.vhd
@@ -13,7 +13,8 @@ architecture sim of simulation is
 	port(
 		input: in signed(17 downto 0);
 		output: out signed(17 downto 0);
-		en: in  std_logic;
+		en: in std_logic;
+		dr: out std_logic;
 		clr: in std_logic;
 		clk: in std_logic
 	);
@@ -22,6 +23,7 @@ architecture sim of simulation is
 	signal input: signed(17 downto 0) := (others => '0');
 	signal output: signed(17 downto 0);
 	signal en:  std_logic := '0';
+	signal dr:  std_logic := '0';
 	signal clr: std_logic := '0';
 	signal clk: std_logic := '0';
 	signal int_input: integer := 0;
@@ -31,6 +33,7 @@ begin
 		input => input,
 		output => output,
 		en => en,
+		dr => dr,
 		clr => clr,
 		clk => clk
 	);
@@ -50,15 +53,21 @@ begin
 
 		-- at 10 ns
 		int_input <= 100000;
-		en <= '1';
+		en <= '0';
 		clr <= '1';
 		wait for 10 ns;
 
 		-- at 20 ns
 		int_input <= 100000;
+		en <= '0';
+		clr <= '0';
+		wait for 10 ns;
+
+		-- at 30 ns
+		int_input <= 100000;
 		en <= '1';
 		clr <= '0';
-		wait for 80 ns;
+		wait for 70 ns;
 
 		-- at 100 ns
 		int_input <= 100000;
diff --git a/averaging_filter/top.vhd b/averaging_filter/top.vhd
index 8241877..6b37e88 100644
--- a/averaging_filter/top.vhd
+++ b/averaging_filter/top.vhd
@@ -9,7 +9,8 @@ entity top is
 	port(
 		input: in signed(17 downto 0);
 		output: out signed(17 downto 0);
-		en: in  std_logic;
+		en: in std_logic;
+		dr: out std_logic;
 		clr: in std_logic;
 		clk: in std_logic
 	);
@@ -24,7 +25,8 @@ architecture func of top is
 	port(
 		input: in signed(data_width-1 downto 0);
 		output: out signed(data_width-1 downto 0);
-		en: in  std_logic;
+		en: in std_logic;
+		dr: out std_logic;
 		clr: in std_logic;
 		clk: in std_logic
 	);
@@ -40,6 +42,7 @@ begin
 		input => input,
 		output => output,
 		en => en,
+		dr => dr,
 		clr => clr,
 		clk => clk
 	);
-- 
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