woods/hdl_cores.git - simple HDL cores

	Commit message (Collapse)	Author	Age	Files	Lines
*	mixed_hdl: add init filesHEAD master	Brian Woods	2023-04-12	1	-0/+44
	This isn't fully mixed but rather it supports VHDL modiles in a verilog simulation. You can't have verilog undernearth the VHDL either. It uses the ghdl (v3 or higher) synth option to synth the VHDL top modules to verilog and then it uses those with Icarus.